Integrated circuits (IC) may be used in a wide range of designs and products. In some designs an IC's input supply voltage may be either fixed or not equal to a required voltage for operation of some of the internal/embedded circuits of the IC. Level shifting circuits and additional dedicated internal/embedded analog circuits may be utilized to provide different voltage levels based on the IC's input supply voltage and control inputs. Furthermore, in some modes of operation different voltage levels may be required for the same circuit.
An example of an IC utilizing voltage shifting is a Non Volatile Memory (NVM) array. An NVM array may be composed of NVM cells, ancillary circuitry, controller and additional circuits which may also require multiple or changing supply levels. For example, a NVM array may require different voltages in different operation modes such as Program, Read and Erase and more. The ancillary circuitry which may include for example: array controls, address decoding circuits, sense amplifiers (SA) configured to determine a value/level of a targeted NVM cell may also be required to operate under changing/alternating supply levels.
Some memory array types may include NVM arrays, floating gate arrays, array of eCT cells, array of MirrorBit cells, charge trapping cells and more. Some transistor types which may be used in ancillary circuitry are Pmos, Nmos, low voltage (LV) Nmos, LV Pmos, high voltage (HV) Nmos and HV Pmos, Zmos, BJT and more. HV transistors/cells may be differentiated from LV transistors/cells by being designed/configured to enable operation in a higher range of voltages across their channel compared to LV cells (for example, between a drain node and a source node of the transistor) and/or across the gate (for example: between their gate and bulk or ground node) and may include a think oxide region compared to LV devices.
Turning now to Prior Art FIG. 1A, depicted is an example level shifter 100A. Example level shifter 100A may operate by using a cross coupled stage 102 including transistors M1 and M2, and an input stage 104 including transistors M3 and M4 and some logical gates. Transistors M1 and M2 are connected to connected to the output supply voltage (OUT) and to the high voltage source VDDH The cross coupled connection between transistors M1, M2, M3 and M4 may act as a feedback circuit, that generates “gain”, when one of the cross coupled transistors (M1 or M2) senses that one of the branches (for example the line between M1 and M3) goes down or up it may cause the other branch (for example between M2 and M4) to change accordingly and may cause the level shifter 100A to switch. The input stage may be connected to the level shifted supply VDDL. VSS is substantially a ground voltage. Depending on design considerations or constraints such as: (a) the ratio between the input voltage (IN) and the output supply voltage (OUT); (b) Breakdown voltages of the transistors and more the M1 and M2 transistors and the M3 and M4 transistors may be designed so that level shifter 100A is caused to flip in response to a change in the input supply (IN). In some embodiments, when the overdrive of the input is much lower than the overdrive of the cross coupled stage 102 (for example a large ratio between IN and OUT) the input transistors (M3 and M4) may be selected to be large (transistors that are not large enough may cause the level shifter not to flip states).
In some embodiments, the NMOS transistors may be prone/suffer from snapback and/or breakdown in which case protection may be required for the NMOS transistors. A typical ratio of the size between one of the cross coupled Pmos transistors to the size of one of the input stage transistors may be 1:5 to 1:10 depending on the technology and on the supply voltage levels. The size of a transistor refers to the width (w) of a transistor divided by the length (l).
Turning to FIG. 1B, depicted is a prior art level shifter 100B including cross coupled Pmos transistors PmosF and PmosG and an input stage including transistors Nmos and Nmos. In this configuration, protection transistors Nmos_brkdnA and Nmos brkdnB with a dynamically controlled gate voltage input (Vgate) may protect input NMOS transistors NmosF and NmosG. Adding this type of protecting may cause the NMOS path to be further degraded/weakened subsequently causing the required input transistors to be even larger than in the architecture of FIG. 1A (when compared to the Pmos transistors). Furthermore, the ratio of the size between one of the cross coupled Pmos transistors to the size of one of the input stage transistors to grow to example ratio 1:15 or more. The size of a transistor refers to the width (w) of a transistor divided by the length (l). Moreover, the current consumption during switching of level shifter 100B may become high due to the weak NMOS path. In some embodiments, when large transistors are used the parasitic capacitance may increase resulting in degraded performance and even higher current consumption. For IC's, where hundreds of level shifter such as level shifter 100B may be required, the area penalty may be considered very significant and the peak current, if multiple level shifter 100Bs are switched together may be very high.
Breakdown of transistors may occur, for example, when a voltage across a transistor (from drain to source or from gate to drain or otherwise) is too high and causes the transistor to be physically destructed and/or be corrupted or inoperable. Referral to a high voltage is in absolute terms (i.e. a negative or positive voltage). Similarly, snapback may occur when the high voltage across the channel is accompanied by a high current and may also lead to breakdown or to induce latchup. Breakdown and Snapback are well known terms and should not be limited to the above description.